(China (Mainland))
Product Summary
The CY2304SI-1 is a zero delay buffer. It enters a power-down state when there are no rising edges on the REF input. In this mode, all outputs are three-stated and the PLL is turned off, resulting in less than 25 µA of current draw. It can accept the same input clock and distribute it in a system. In this case, the skew between the outputs of two devices is guaranteed to be less than 500 ps.
Parametrics
CY2304SI-1 absolute maximum ratings: (1)supply voltage to ground potential: -0.5 to 7V; (2)DC input voltage: -0.5 to VDD+0.5V; (3)DC input voltage REF: -0.5 to 7V; (4)storage temperature: -65 to 150℃; (5)junction temperature: 150℃; (6)static discharge voltage: >2000V.
Features
CY2304SI-1 features: (1)Zero input-output propagation delay, adjustable by capacitive load on FBK input; (2)Multiple configurations – see “Available Configurations” table; (3)Multiple low-skew outputs; (4)10-MHz to 133-MHz operating range; (5)Low jitter, less than 200 ps cycle-cycle; (6)Space-saving 8-pin 150-mil SOIC package; (7)3.3V operation; (8)Industrial temperature available.
Diagrams
| Image | Part No | Mfg | Description |  |
Pricing (USD) |
Quantity | ||||||||||||
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 CY2304SI-1 |
Cypress Semiconductor |
Phase Locked Loops (PLL) 3.3VZDB COM |
Data Sheet |
Negotiable |
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| Image | Part No | Mfg | Description | |
Pricing (USD) |
Quantity | ||||||||||||
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CY2300 |
Other |
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Data Sheet |
Negotiable |
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CY2300SXC |
Cypress Semiconductor |
Phase Locked Loops (PLL) 3.3VZDB COM |
Data Sheet |
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CY2300SXCT |
Cypress Semiconductor |
Phase Locked Loops (PLL) 3.3VZDB COM |
Data Sheet |
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CY2302 |
Other |
|
Data Sheet |
Negotiable |
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CY23020-1 |
Other |
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Data Sheet |
Negotiable |
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CY23020LFI-3 |
Cypress Semiconductor |
Phase Locked Loops (PLL) 400MHz IND Zero Delay Buffer |
Data Sheet |
Negotiable |
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