AD9254BCPZ-150

Product Summary

The AD9254BCPZ-1501 is a monolithic, single 1.8 V supply, 14-bit, 150 MSPS analog-to-digital converter (ADC), featuring high performance sample-and-hold amplifier (SHA) and on-chip voltage reference. AD9254BCPZ-1501 uses a multistage differential pipeline architecture with output error correction logic to provide 14-bit accuracy at 150 MSPS data rates and guarantees no missing codes over the full operating temperature range. The main applications of AD9254BCPZ-1501 are (1)Ultrasound equipment ; (2)IF sampling in communications receivers ; (3)CDMA2000, WCDMA, TD-SCDMA, and WiMax ; (4)Battery-powered instruments ; (5)Hand-held scopemeters ; (6)Low cost digital oscilloscopes ; (7)Macro, micro, and pico cell infrastructure, etc.

Parametrics

AD9254BCPZ-150 absolute maximum ratings: (1)AVDD to AGND:-0.3 V to +2.0 V ; (2)DRVDD to DGND: -0.3 V to +3.9 V ; (3)AGND to DGND: -0.3 V to +0.3 V ; (4)AVDD to DRVDD: -3.9 V to +2.0 V ; (5)D0 through D13 to DGND:-0.3 V to DRVDD + 0.3 V ; (6)DCO to DGND:-0.3 V to DRVDD + 0.3 V ; (7)OR to DGND: -0.3 V to DRVDD + 0.3 V ; (8)CLK+ to AGND: -0.3 V to +3.9 V ; (9)CLK- to AGND: -0.3 V to +3.9 V ; (10)VIN+ to AGND: -0.3 V to AVDD + 0.2 V ; (11)VIN- to AGND: -0.3 V to AVDD + 0.2 V ; (12)VREF to AGND: -0.3 V to AVDD + 0.2 V ; (13)SENSE to AGND: -0.3 V to AVDD + 0.2 V ; (14)REFT to AGND: -0.3 V to AVDD + 0.2 V ; (15)REFB to AGND: -0.3 V to AVDD + 0.2 V ; (16)SDIO/DCS to DGND:-0.3 V to DRVDD + 0.3 V ; (17)PDWN to AGND:-0.3 V to +3.9 V ; (18)CSB to AGND:-0.3 V to +3.9 V ; (19)SCLK/DFS to AGND:-0.3 V to +3.9 V ; (20)OEB to AGND:-0.3 V to +3.9 V; (21)Storage Temperature Range:–65°C to +125°C ; (22)Operating Temperature Range:–40°C to +85°C ; (23)Lead Temperature (Soldering 10 Sec):300°C ; (24)Junction Temperature:150°C.

Features

AD9254BCPZ-15 features: (1)1.8 V analog supply operation ; (2)1.8 V to 3.3 V output supply ; (3)SNR = 71.8 dBc (72.8 dBFS) to 70 MHz input ; (4)SFDR = 84 dBc to 70 MHz input ; (5)Low power: 430 mW @ 150 MSPS ; (6)Differential input with 650 MHz bandwidth ; (7)On-chip voltage reference and sample-and-hold amplifier ; (8)DNL = ±0.4 LSB ; (9)Flexible analog input: 1 V p-p to 2 V p-p range ; (10)Offset binary, Gray code, or twos complement data format ; (11)Clock duty cycle stabilizer ; (12)Data output clock ; (13)Serial port control ; (14)Built-in selectable digital test pattern generation ; (15)Programmable clock and data alignment.

Diagrams