Product Summary
The HYB25D256800CEL-6 is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a quad-bank DRAM. The HYB25D256800CEL-6 uses a double-data-rate architecture to achieve high-speedoperation. The double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. The HYB25D256800CEL-6 provides for programmable Read or Write burst lengths of 2, 4 or 8 locations. An Auto Precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access.
Parametrics
HYB25D256800CEL-6 absolute maximum ratings: (1)Voltage on I/O pins relative to Vss: –0.5 to VDDQ+0.5 V; (2)Voltage on inputs relative to Vss: –1 to +3.6 V; (3)Voltage on VDD supply relative to Vss: –1 to +3.6 V; (4)Voltage on VDDQ supply relative to Vss: –1 to +3.6 V; (5)Operating temperature (ambient): 0 to +70 °C; (6)Storage temperature (plastic): -55 to +150°C; (7)Power dissipation: 1.5W; (8)Short circuit output current: 50mA.
Features
HYB25D256800CEL-6 features: (1)Double data rate architecture: two data transfers per clock cycle; (2)Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at thereceiver ; (3)DQS is edge-aligned with data for reads and is center-aligned with data for writes; (4)Four internal banks for concurrent operation; (5)Data mask (DM) for write data; (6)DLL aligns DQ and DQS transitions with CK transitions; (7)Auto Precharge option for each burst access; (8)Auto Refresh and Self Refresh Modes.
Diagrams
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